The present invention relates to a semiconductor device manufacturing method and, more particularly, to a semiconductor device manufacturing method including a burn-in test process and a technique effectively applicable to a program used to perform the manufacturing method.
A semiconductor device manufacturing process includes a test process in which a burn-in (hereinafter also referred to as “BI”) test (acceleration test) is performed. In a burn-in test, each semiconductor device is, for example, subjected to a high temperature and a high voltage for a predetermined amount of time for the purpose of removing semiconductor devices likely to develop initial failure.
In Published Japanese Translation of a PCT Application No. 2008-544213 (patent literature 1), a technique is disclosed in which, based on some information, the chips formed on a semiconductor wafer are sorted into two groups, and the chips in one of the two groups are subjected to a long stress test and the chips in the other group are subjected to a short stress test. In the technique disclosed in A. Nahar, R. Daasch, S. Subramaniam, “Burn-In Reduction Using Principal Component Analysis,” IEEE International Test Conference 2005 (non-patent literature 1), an optimum time length of a burn-in test is determined by making principal component analysis based on past burn-in test results and forecasting a fail time. Also, in the technique disclosed in N. Sumikawa, L.-C. Wang, M. S. Abadir, “An Experiment of Burn-In Time Reduction Based On Parametric Test Analysis,” IEEE International Test Conference 2012 (non-patent literature 2), by analyzing results of a short burn-in test, whether an additional burn-in test is required is determined for each lot.